REVISION
Definition in file CODEC_config.c.
#include "../SYSTEM/sys_hardware.h"
#include "../SYSTEM/sys_main.h"
#include "codec.h"
#include "codec_assert.h"
#include "../FMXMIT/xmit_inc.h"
Include dependency graph for CODEC_config.c:
Go to the source code of this file.
Functions | |
| void | CODEC_config (COP_MODE eMode) |
| Function initializes the codec given the inputs. | |
| void | CODEC_hpVolume (int volume) |
| Function controls headphone volume. | |
| void | CODEC_gain (void) |
| Function controls channel gain. | |
| void | CODEC_setHandle (PFPCMGET getHdl, PFPCMPUT putHdl, PFPCMDEC decode, PFPCMENC encode) |
| Function sets up the PCM get/put handle. | |
| void | CODEC_power (COP_MODE eMode) |
| Function controls the power ON/OFF of the codec DAC and ADC. | |
| void | CODEC_mute (void) |
| Function mute the codec interface. | |
| void | CODEC_unmute (void) |
| Function unmute the codec interface. | |
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Function initializes the codec given the inputs. This function will set up the corresponding DMA engines and initialize McBSP. DAC and ADC of the Codec will also be set to given state determined by eMode.
Definition at line 56 of file CODEC_config.c. References CODEC_power(), st_PCM::codecMode, st_PCM::flag, GEN_zeroOut(), st_PCM::getFunc, McBSP_init(), st_PCM::newGetFunc, st_PCM::newPutFunc, st_PCM::pipe, PIPE_reset(), PIPE_writeNext(), and st_PCM::putFunc. Referenced by AUDIO_start(). 00057 {
00058 if(Pcm.codecMode != eMode)
00059 {
00060 /* Halt DMA3 and CODEC_McBSP */
00061 CODEC_haltPcm();
00062 Pcm.codecMode = eMode;
00063 Pcm.getFunc = Pcm.newGetFunc;
00064 Pcm.putFunc = Pcm.newPutFunc;
00065
00066 CODEC_power(eMode);
00067
00068 if( (eMode != COP_MIC_RECORD) )
00069 {
00070 /* Reset the pipe object, initialize to zero frames. */
00071 PIPE_reset(&Pcm.pipe);
00072 GEN_zeroOut((UINT16 *)Pcm.pipe.WrFrame.Frame, PCM_PIPE_FRAMELEN);
00073
00074 PIPE_writeNext(&Pcm.pipe);
00075 GEN_zeroOut((UINT16 *)Pcm.pipe.WrFrame.Frame, PCM_PIPE_FRAMELEN);
00076
00077 PIPE_writeNext(&Pcm.pipe);
00078 Pcm.flag |= HAVE_NEXT_BLOCK;
00079 }
00080
00081 /* Initialize the pcm globals */
00082 Pcm.flag &= ~(UPPER_HALF_BUF|STARTED_NEXT_BLOCK);
00083 Pcm.flag |= IS_MUTED;
00084
00085 /* DMA3/DMA4 has higher priority, Interrupt source selected. */
00086 DMPREC |= 0x1840;
00087
00088 /* Set the FREE bit so that transfers not stop with emulator */
00089 //DMPREC |= 0x8000;
00090
00091
00092 /* Setup DMA3 to connect to McBSP transmitter to send out audio data. */
00093
00094 /* point to DMSRC3 register */
00095 DMSBAR = DMSRC3_SUBADDR;
00096
00097 /* DMSRC3 = Transmit buffer pong address */
00098 DMSBAI = (int)Pcm.pipe.RdFrame.Frame;
00099
00100 /* DMDST3 = CODEC_McBSP data transmit register */
00101 DMSBAI = MCBSP_DXR1_ADDR(CODEC_McBSP);
00102
00103 /* DMCTR3 = Transmit buffer size (2 words in sample--left/right)
00104 ** 2 words per frame, 64 frames per block.
00105 */
00106 DMSBAI = 1;
00107
00108 /* Modification of CODEC_McBSP definition will cause changes here. */
00109 /* DMSFC3 = McBSP0 transmit sync event frames = # of samples */
00110 DMSBAI = 0x2000+(PCM_CHANNEL_BUFLEN-1);
00111
00112
00113 /* DMMCR3 = Auto-init,
00114 ** interrupt at block complete,
00115 ** DMA interrupt enabled,
00116 ** decrement mode (auto-init)
00117 */
00118 DMSBAI = 0xc541;
00119
00120 DMSBAR = DMIDX0_SUBADDR;
00121
00122
00123 /* DMIDX0 = step to next sample in frame */
00124 DMSBAN = PCM_CHANNEL_BUFLEN;
00125
00126 DMSBAR = DMFRI0_SUBADDR;
00127
00128 /* DMFRI0 = step to next frame */
00129 DMSBAN = (unsigned short)(1 - PCM_CHANNEL_BUFLEN);
00130
00131
00132 DMSBAR = DMGSA_SUBADDR;
00133
00134 /* DMGSA = Transmit buffer pong address */
00135 DMSBAI = (int)Pcm.pipe.RdFrame.NextFrame;
00136
00137
00138 /* DMGDA = McBSP0 data transmit register */
00139 DMSBAI = MCBSP_DXR1_ADDR(CODEC_McBSP);
00140
00141 /* DMGCR = Transmit buffer size (2 words in sample--left/right) */
00142 DMSBAI = 1;
00143
00144
00145 /* DMGFR = McBSP0 transmit sync event frames = # of samples */
00146 DMSBAI = 0x2000+(PCM_CHANNEL_BUFLEN-1);
00147
00148
00149 /* Setup DMA4 to connect to McBSP receiver to receive audio data. */
00150 DMSBAR = DMSRC4_SUBADDR;
00151
00152 /* DMA source: CODEC_McBSP receiver address */
00153 DMSBAI = MCBSP_DRR1_ADDR(CODEC_McBSP);
00154
00155 /* DMA destination: BUF_input, which MUST be a circular buffer.*/
00156 DMSBAI = (int)BUF_output;
00157
00158 /* DMCTR4 = Transmit buffer size (2 words in sample--left/right) */
00159 DMSBAI = 4*PCM_CHANNEL_BUFLEN;
00160
00161
00162 /* Modification of CODEC_McBSP definition will cause changes here. */
00163 /* DMSFC4 = McBSP0 receiver sync event */
00164 DMSBAI = 0x1000;
00165
00166
00167 /* DMMCR4 = No Auto-init
00168 ** DMA in ABU mode
00169 ** DMA interrupt occurs at half-buffer filled
00170 ** DMA index address autoincrement step: one word
00171 ** DMA in single word mode
00172 ** DMA postincrement wiht index offset, similiar with DMA3.
00173 */
00174 DMSBAI = 0x7045;
00175
00176
00177 /* clear the DMA3/4 interrupt here to prevent malfunction. */
00178 IFR |= 0x1800;
00179
00180 /* Unmute Codec & start DMA3/4. */
00181 CODEC_setActiveState(eMode);
00182
00183 /* Initialize CODEC_McBSP. */
00184 McBSP_init(CODEC_McBSP, /* port number */
00185
00186 /* Digital Loop back, just for testing. */
00187 //FIELD_VAL(DLB, 1, 1 )| /* spcr1 */
00188
00189 FIELD_VAL(RINTM, RINTM_SZ, INTM_RDY )| /* spcr1 */
00190 FIELD_VAL(RJUST, RJUST_SZ, RXJUST_RJSE )| /* spcr1 */
00191 FIELD_VAL(CLKSTP, CLKSTP_SZ, 0 )| /* spcr1 */
00192 FIELD_VAL(RRST, 1, 1 ), /* spcr1 - receiver is enabled */
00193
00194 FIELD_VAL(FREE, 1, 1 )| /* spcr2 - free running mode is enabled */
00195 FIELD_VAL(SOFT, 1, 1 )| /* spcr2 - don't care. */
00196 FIELD_VAL(XINTM, XINTM_SZ, INTM_RDY )| /* spcr2 */
00197 FIELD_VAL(XRST, 1, 1 )| /* spcr2 - transmittor is enabled */
00198 FIELD_VAL(GRST, 1, 1 )| /* spcr2 */
00199 FIELD_VAL(FRST, 1, 0 ), /* spcr2 - Frame sync is provided by Codec */
00200
00201 FIELD_VAL(RWDLEN1, RWDLEN1_SZ, WORD_LENGTH_16 )| /* rcr1 - 16 bits per word */
00202 FIELD_VAL(RFRLEN1, RFRLEN1_SZ, 1 ), /* rcr1 - 2 words per frame */
00203
00204 FIELD_VAL(RDATDLY, RDATDLY_SZ, DATA_DELAY0 )| /* rcr2 - N/A */
00205 FIELD_VAL(RFIG, 1, FRAME_IGNORE )| /* rcr2 - N/A */
00206 FIELD_VAL(RCOMPAND, RCOMPAND_SZ,NO_COMPAND_MSB_1ST )| /* rcr2 - N/A */
00207 FIELD_VAL(RWDLEN2, RWDLEN2_SZ, WORD_LENGTH_16 )| /* rcr2 - N/A */
00208 FIELD_VAL(RFRLEN2, RFRLEN2_SZ, 0 )| /* rcr2 - N/A */
00209 FIELD_VAL(RPHASE, 1, SINGLE_PHASE ), /* rcr2 - N/A */
00210
00211 FIELD_VAL(XWDLEN1, XWDLEN1_SZ, WORD_LENGTH_16 )| /* xcr1 - 16-bit words in the first phase */
00212 FIELD_VAL(XFRLEN1, XFRLEN1_SZ, 1 ), /* xcr1 - 2 words in the first phase */
00213
00214 FIELD_VAL(XDATDLY, XDATDLY_SZ, DATA_DELAY0 )| /* xcr2 - delay data clocks from frame sync. */
00215 FIELD_VAL(XFIG, 1, FRAME_IGNORE )| /* xcr2 - ignore extraneous frame syncs */
00216 FIELD_VAL(XCOMPAND, XCOMPAND_SZ,NO_COMPAND_MSB_1ST )| /* xcr2 - MSB align data (no companding) */
00217 FIELD_VAL(XWDLEN2, XWDLEN2_SZ, WORD_LENGTH_16 )| /* xcr2 - N/A */
00218 FIELD_VAL(XFRLEN2, XFRLEN2_SZ, 0 )| /* xcr2 - N/A */
00219 FIELD_VAL(XPHASE, 1, SINGLE_PHASE ), /* xcr2 - single phase frame */
00220
00221 0, /* srgr1 - N/A */
00222 0, /* srgr2 - N/A */
00223
00224 FIELD_VAL(RMCM, 1, 0 ), /* mcr1 - all 128 RX channels are enabled */
00225 FIELD_VAL(XMCM, XMCM_SZ, 0 ), /* mcr2 - all 128 TX channels are enabled */
00226 0, /* rcera - N/A */
00227 0, /* rcerb - N/A */
00228 0, /* xcera - N/A */
00229 0, /* xcerb - N/A */
00230
00231 FIELD_VAL(CLKRP, 1, CLKR_POL_FALLING )| /* pcr - N/A */
00232 FIELD_VAL(CLKXP, 1, CLKX_POL_FALLING )| /* pcr - transmit data sampled on falling edge of CLKX */
00233 FIELD_VAL(FSRP, 1, FSYNC_POL_HIGH )| /* pcr - N/A */
00234 FIELD_VAL(FSXP, 1, FSYNC_POL_HIGH )| /* pcr - frame sync pulse (FSX) is active high */
00235 FIELD_VAL(CLKRM, 1, CLK_MODE_EXT )| /* pcr - CLKR is an input pin */
00236 FIELD_VAL(CLKXM, 1, CLK_MODE_EXT )| /* pcr - CLKX is an intput pin */
00237 FIELD_VAL(FSRM, 1, FSYNC_MODE_EXT )| /* pcr - FSR is an input pin */
00238 FIELD_VAL(FSXM, 1, FSYNC_MODE_EXT ) /* pcr - FSX is an input */
00239
00240 );
00241
00242 // Wait till codec interface stablized before bringing up volume. We'll
00243 // lose 50ms music here.
00244 //if( eMode & (COP_MUSIC|COP_TUNER|COP_ILINK|COP_LINE_RECORD|COP_FM_RECORD|COP_AUTOSCAN|COP_TUNER_MIC) )
00245 //{
00246 // SYS_delayMicrosecond(50000);
00247 // CODEC_hpVolume(sysParam.volume);
00248 //}
00249 }
00250 else
00251 {
00252 SWI_disable();
00253 Pcm.getFunc = Pcm.newGetFunc;
00254 Pcm.putFunc = Pcm.newPutFunc;
00255 SWI_enable();
00256 }
00257 }
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Function controls headphone volume.
Definition at line 267 of file CODEC_config.c. References CODEC__spiWrite(). Referenced by CODEC_mute(), CODEC_unmute(), UI_CSF_volume(), and UI_PSF_radio(). 00268 {
00269 /* Simultaneously update left/right channel???. */
00270 if(volume) volume += VOLUME_OFFSET;
00271
00272 CODEC__spiWrite(AIC23REG_LHDPHONE | 0x100 | volume);
00273 //CODEC__spiWrite(AIC23REG_RHDPHONE | 0x100 | volume);
00274 }
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Function controls the power ON/OFF of the codec DAC and ADC.
Definition at line 334 of file CODEC_config.c. References CODEC__spiWrite(), COP_AUTOSCAN, COP_FM_RECORD, COP_FMXMIT, COP_ILINK, COP_LINE_RECORD, COP_MIC_RECORD, COP_MUSIC, COP_POWERDOWN, COP_TUNER, and COP_TUNER_MIC. Referenced by CODEC_config(). 00335 {
00336 // Shut down DMA before Codec to prevent "pops".
00337 CODEC_setActiveState(COP_POWERDOWN);
00338
00339 if(eMode & COP_POWERDOWN)
00340 {
00341 // Turn off DSP clock out, disable codec clock.
00342 CPLD_CODECClk(2);
00343 }
00344
00345 else if( eMode & (COP_ILINK|COP_FMXMIT) )
00346 {
00347 /* Choose to use internal clock. */
00348 CPLD_CODECClk(1);
00349 }
00350
00351 // Always use external clock else, thus to disable clock out pin and
00352 // conserve power.
00353 else
00354 {
00355 /* Choose to use external clock. */
00356 CPLD_CODECClk(0);
00357 }
00358
00359 switch(eMode)
00360 {
00361 //case COP_POWERDOWN:
00362 // Do NOT power down codec, thus to prevent power up pop.
00363 // break;
00364
00365 case COP_MIC_RECORD:
00366 //CODEC__spiWrite(AIC23REG_RESET);
00367 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x069);
00368 CODEC__spiWrite(AIC23REG_APATH | 0x004);
00369 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00370 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00371 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00372 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00373
00374 //SYS_delayMicrosecond(200000);
00375 break;
00376
00377 case COP_TUNER_MIC:
00378 //CODEC__spiWrite(AIC23REG_RESET);
00379 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x060);
00380 CODEC__spiWrite(AIC23REG_APATH | 0x0015);
00381 CODEC__spiWrite(AIC23REG_DPATH | 0x0001);
00382 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00383 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00384 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00385 break;
00386
00387 case COP_AUTOSCAN:
00388 //CODEC__spiWrite(AIC23REG_RESET);
00389 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00390 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00391 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00392 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00393 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00394 CODEC__spiWrite(AIC23REG_LLNVOL | 0x11f);
00395 // 0dB headphone output.
00396 CODEC__spiWrite(AIC23REG_LHDPHONE | 0x100 | 0x079);
00397 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00398 break;
00399
00400 case COP_TUNER:
00401 //CODEC__spiWrite(AIC23REG_RESET);
00402 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00403 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00404 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00405 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00406 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00407 CODEC__spiWrite(AIC23REG_LLNVOL | 0x11f);
00408 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00409 break;
00410
00411 case COP_LINE_RECORD:
00412 //CODEC__spiWrite(AIC23REG_RESET);
00413 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00414 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00415 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00416 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00417 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00418 CODEC__spiWrite(AIC23REG_LLNVOL | 0x117);
00419 CODEC__spiWrite(AIC23REG_RLNVOL | 0x117);
00420 // 0dB headphone output.
00421 CODEC__spiWrite(AIC23REG_LHDPHONE | 0x100 | 0x079);
00422 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00423 break;
00424
00425 case COP_FM_RECORD:
00426 //CODEC__spiWrite(AIC23REG_RESET);
00427 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00428 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00429 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00430 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00431 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00432 CODEC__spiWrite(AIC23REG_LLNVOL | 0x11f);
00433 CODEC__spiWrite(AIC23REG_RLNVOL | 0x11f);
00434 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00435 break;
00436
00437 case COP_MUSIC:
00438 //CODEC__spiWrite(AIC23REG_RESET);
00439 #ifdef MIXER_SUPPORT
00440 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x061);
00441 CODEC__spiWrite(AIC23REG_APATH | 0x015);
00442 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00443 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00444 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00445 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00446 #else
00447 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x067);
00448 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00449 CODEC__spiWrite(AIC23REG_DPATH | 0x000);
00450 CODEC__spiWrite(AIC23REG_SRC | 0x23);
00451 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x63);
00452 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00453 #endif
00454 break;
00455
00456 case COP_ILINK:
00457 CODEC__spiWrite(AIC23REG_RESET);
00458 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00459 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00460 CODEC__spiWrite(AIC23REG_DPATH | 0x001);
00461 CODEC__spiWrite(AIC23REG_SRC | 0x3f);
00462 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x43);
00463 CODEC__spiWrite(AIC23REG_LLNVOL | 0x17);
00464 CODEC__spiWrite(AIC23REG_RLNVOL | 0x17);
00465 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00466 break;
00467
00468 case COP_FMXMIT:
00469 #ifdef MIXER_SUPPORT
00470 CODEC__spiWrite(AIC23REG_RESET);
00471 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x061);
00472 CODEC__spiWrite(AIC23REG_APATH | 0x014);
00473 CODEC__spiWrite(AIC23REG_DPATH | 0x001);
00474 CODEC__spiWrite(AIC23REG_SRC | 0x3f);
00475 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x43);
00476 CODEC__spiWrite(AIC23REG_LLNVOL | 0x17);
00477 CODEC__spiWrite(AIC23REG_RLNVOL | 0x17);
00478 CODEC__spiWrite(AIC23REG_LHDPHONE | 0x100);
00479 CODEC__spiWrite(AIC23REG_RHDPHONE | 0x100);
00480 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00481 #else
00482 CODEC__spiWrite(AIC23REG_RESET);
00483 CODEC__spiWrite(AIC23REG_PWRDOWN | 0x062);
00484 CODEC__spiWrite(AIC23REG_APATH | 0x012);
00485 CODEC__spiWrite(AIC23REG_DPATH | 0x001);
00486 CODEC__spiWrite(AIC23REG_SRC | 0x3f);
00487 CODEC__spiWrite(AIC23REG_DAUDIOI | 0x43);
00488 CODEC__spiWrite(AIC23REG_LLNVOL | 0x17);
00489 CODEC__spiWrite(AIC23REG_RLNVOL | 0x17);
00490 CODEC__spiWrite(AIC23REG_LHDPHONE | 0x100);
00491 CODEC__spiWrite(AIC23REG_RHDPHONE | 0x100);
00492 CODEC__spiWrite(AIC23REG_DIACTV | 0x01);
00493 #endif
00494 break;
00495 }
00496 }
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Function sets up the PCM get/put handle.
Definition at line 313 of file CODEC_config.c. References st_PCM::decode, st_PCM::encode, st_PCM::newGetFunc, and st_PCM::newPutFunc. Referenced by AUDIO_start(). 00317 {
00318 if(getHdl) Pcm.newGetFunc = getHdl;
00319 else Pcm.newGetFunc = CODEC__defaultPcmGet;
00320 if(putHdl) Pcm.newPutFunc = putHdl;
00321 else Pcm.newPutFunc = CODEC__defaultPcmPut;
00322 if(decode) Pcm.decode = decode;
00323 if(encode) Pcm.encode = encode;
00324 }
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1.3.9.1