00001 /***************************************************************************** 00002 C H E A D E R F I L E 00003 00004 Copyright (c) 2003 Neuros Audio LLC, All rights reserved. 00005 00006 ******************************************************************************/ 00007 00016 00017 #ifndef C54REGS__H 00018 #define C54REGS__H 00019 00020 /*---------------------------------------------------------------------------*/ 00021 #ifdef __cplusplus 00022 extern "C" { 00023 #endif 00024 00025 /*-- HEADER FILE INCLUDES ---------------------------------------------------*/ 00026 #include "stdio.h" 00027 #include "stdlib.h" 00028 00029 /*-- SHARED DEFINITIONS -----------------------------------------------------*/ 00030 00031 // Global Register Address defined. 00032 #define DMPREC_ADDR 0x0054 /*DMA priority control register address*/ 00033 #define DMSBAR_ADDR 0x0055 /*DMA sub-bank address reigister address*/ 00034 #define DMSBAI_ADDR 0x0056 /*DMA auto-increment sub-bank data register address*/ 00035 #define DMSBAN_ADDR 0x0057 /*DMA no-auto-increment sub-bank data register address*/ 00036 #define DMSRC0_SUBADDR 0 /*DMSRC0 register sub-bank index address */ 00037 #define DMDST0_SUBADDR 1 /*DMDST0 register sub-bank index address */ 00038 #define DMCTR0_SUBADDR 2 /*DMACTR0 register sub-bank index address*/ 00039 #define DMSFC0_SUBADDR 3 /*DMSFC0 register sub-bank index address */ 00040 #define DMMCR0_SUBADDR 4 /*DMMCR0 register sub-bank index address */ 00041 #define DMSRC1_SUBADDR 5 /*DMSRC1 register sub-bank index address */ 00042 #define DMDST1_SUBADDR 6 /*DMDST1 register sub-bank index address */ 00043 #define DMCTR1_SUBADDR 7 /*DMCTR1 register sub-bank index address */ 00044 #define DMSFC1_SUBADDR 8 /*DMSFC1 register sub-bank index address */ 00045 #define DMMCR1_SUBADDR 9 /*DMMCR1 register sub-bank index address */ 00046 #define DMSRC2_SUBADDR 10 /*DMSRC2 register sub-bank index address */ 00047 #define DMDST2_SUBADDR 11 /*DMDST2 register sub-bank index address */ 00048 #define DMCTR2_SUBADDR 12 /*DMCTR2 register sub-bank index address */ 00049 #define DMSFC2_SUBADDR 13 /*DMSFC2 register sub-bank index address */ 00050 #define DMMCR2_SUBADDR 14 /*DMMCR2 register sub-bank index address */ 00051 #define DMSRC3_SUBADDR 15 /*DMSRC3 register sub-bank index address */ 00052 #define DMDST3_SUBADDR 16 /*DMDST3 register sub-bank index address */ 00053 #define DMCTR3_SUBADDR 17 /*DMCTR3 register sub-bank index address */ 00054 #define DMSFC3_SUBADDR 18 /*DMSFC3 register sub-bank index address */ 00055 #define DMMCR3_SUBADDR 19 /*DMMCR3 register sub-bank index address */ 00056 #define DMSRC4_SUBADDR 20 /*DMSRC4 register sub-bank index address */ 00057 #define DMDST4_SUBADDR 21 /*DMDST4 register sub-bank index address */ 00058 #define DMCTR4_SUBADDR 22 /*DMCTR4 register sub-bank index address */ 00059 #define DMSFC4_SUBADDR 23 /*DMSFC4 register sub-bank index address */ 00060 #define DMMCR4_SUBADDR 24 /*DMMCR4 register sub-bank index address */ 00061 #define DMSRC5_SUBADDR 25 /*DMSRC5 register sub-bank index address */ 00062 #define DMDST5_SUBADDR 26 /*DMDST5 register sub-bank index address */ 00063 #define DMCTR5_SUBADDR 27 /*DMCTR5 register sub-bank index address */ 00064 #define DMSFC5_SUBADDR 28 /*DMSFC5 register sub-bank index address */ 00065 #define DMMCR5_SUBADDR 29 /*DMMCR5 register sub-bank index address */ 00066 #define DMSRCP_SUBADDR 30 /*DMSRCP register sub-bank index address */ 00067 #define DMDSTP_SUBADDR 31 /*DMDSTP register sub-bank index address */ 00068 #define DMIDX0_SUBADDR 32 /*DMIDX0 register sub-bank index address */ 00069 #define DMIDX1_SUBADDR 33 /*DMIDX1 register sub-bank index address */ 00070 #define DMFRI0_SUBADDR 34 /*DMFRI0 register sub-bank index address */ 00071 #define DMFRI1_SUBADDR 35 /*DMFRI1 register sub-bank index address */ 00072 #define DMGSA_SUBADDR 36 /*DMGSA register sub-bank index address */ 00073 #define DMGDA_SUBADDR 37 /*DMGDA register sub-bank index address */ 00074 #define DMGCR_SUBADDR 38 /*DMGCR register sub-bank index address */ 00075 #define DMGFR_SUBADDR 39 /*DMGFR register sub-bank index address */ 00076 00077 #define IMR_ADDR 0x0000 /*IMR register address*/ 00078 #define IFR_ADDR 0x0001 /*0x0001 IFR register address*/ 00079 #define ST1_ADDR 0x0007 /* 0x0007 ST1 register address */ 00080 #define TIM_ADDR 0x0024 /*TIM register address*/ 00081 #define PRD_ADDR 0x0025 /*PRD register address*/ 00082 #define TCR_ADDR 0x0026 /*TCR register address*/ 00083 #define SWWSR_ADDR 0x0028 /*SWWSR register address*/ 00084 #define BSCR_ADDR 0x0029 /*BSCR register address*/ 00085 #define SWCR_ADDR 0x002b /*SWCR register address*/ 00086 #define HPIC_ADDR 0x002c /*HPIC register address*/ 00087 #define GPIOCR_ADDR 0x003c /*GPIO Control register address */ 00088 #define GPIOSR_ADDR 0x003d /*GPIO Status register address */ 00089 #define CLKMD_ADDR 0x0058 /*Clock mode register address */ 00090 #define PMST_ADDR 0x001d /*PMST address register */ 00091 00092 #define SPSA2_ADDR 0x0034 /* Serial port sub address register #2 */ 00093 #define SPSA1_ADDR 0x0048 /* Serial port sub address register #1 */ 00094 #define SPSA0_ADDR 0x0038 /* Serial port sub address register #0 */ 00095 #define SPCR1 0x0000 /* serial port control register 1, sub address */ 00096 #define SPCR2 0x0001 /* Serial port control register 2, sub address */ 00097 #define RCR1 0x0002 /* receive control register 1 */ 00098 #define RCR2 0x0003 /* receive control register 2 */ 00099 #define XCR1 0x0004 /* transmit control register 1 */ 00100 #define XCR2 0x0005 /* transmit control register 2 */ 00101 #define SRGR1 0x0006 /* sample rate generator register 1 */ 00102 #define SRGR2 0x0007 /* sample rate generator register 2 */ 00103 #define MCR1 0x0008 /* multichannel register 1 */ 00104 #define MCR2 0x0009 /* multichannel register 2 */ 00105 #define RCERA 0x000a /* receive channel enable register partition A */ 00106 #define RCERB 0x000b /* receive channel enable register partition B */ 00107 #define XCERA 0x000c /* transmit channel enable register partition A */ 00108 #define XCERB 0x000d /* transmit channel enable register partition B */ 00109 #define PCR 0x000e /* Pin control register for serial port */ 00110 #define SPACC2_ADDR 0x0035 /* serial port 2, sub address access point */ 00111 #define SPACC1_ADDR 0x0049 /* serial port 1, sub address access point */ 00112 #define SPACC0_ADDR 0x0039 /* serial port 0, sub address access point */ 00113 00114 00115 // Generic Global Constants. 00116 #define DMA2_INT 0x0400 /*DMA channel 2 interrupt mask*/ 00117 #define DMA3_INT 0x0800 /*DMA channel 3 interrupt mask*/ 00118 #define DMA4_INT 0x1000 /*DMA channel 4 Interrupt mask*/ 00119 #define EXT0_INT 0x0001 /*External interrupt 0 mask*/ 00120 #define EXT1_INT 0x0002 /*External interrupt 1 mask*/ 00121 #define EXT2_INT 0x0004 /*External interrupt 1 mask*/ 00122 #define EXT3_INT 0x0100 /*External interrupt 3 mask*/ 00123 00124 // Register Operation Macro. 00125 #define DMPREC *(volatile unsigned int *)(DMPREC_ADDR) 00126 #define DMSBAR *(volatile unsigned int *)(DMSBAR_ADDR) 00127 #define DMSBAI *(volatile unsigned int *)(DMSBAI_ADDR) 00128 #define DMSBAN *(volatile unsigned int *)(DMSBAN_ADDR) 00129 #define IMR *(volatile unsigned int *)(IMR_ADDR) 00130 #define IFR *(volatile unsigned int *)(IFR_ADDR) 00131 #define ST1 *(volatile unsigned int *)(ST1_ADDR) 00132 #define PRD *(volatile unsigned int *)(PRD_ADDR) 00133 #define TIM *(volatile unsigned int *)(TIM_ADDR) 00134 #define TCR *(volatile unsigned int *)(TCR_ADDR) 00135 #define SWWSR *(volatile unsigned int *)(SWWSR_ADDR) 00136 #define BSCR *(volatile unsigned int *)(BSCR_ADDR) 00137 #define SWCR *(volatile unsigned int *)(SWCR_ADDR) 00138 #define HPIC *(volatile unsigned int *)(HPIC_ADDR) 00139 #define CLKMD *(volatile unsigned int *)(CLKMD_ADDR) 00140 #define PMST *(volatile unsigned int *)(PMST_ADDR) 00141 #define SPSA1 *(volatile unsigned int *)(SPSA1_ADDR) 00142 #define SPSA2 *(volatile unsigned int *)(SPSA2_ADDR) 00143 #define SPACC1 *(volatile unsigned int *)(SPACC1_ADDR) 00144 #define SPACC2 *(volatile unsigned int *)(SPACC2_ADDR) 00145 00146 // General Purpose I/O. 00147 #define GPIOCR *(volatile unsigned int *)(GPIOCR_ADDR) 00148 #define GPIOSR *(volatile unsigned int *)(GPIOSR_ADDR) 00149 00150 extern int CPY_SWWSR; 00151 00152 /*-- FUNCTION PROTOTYPES ----------------------------------------------------*/ 00153 00154 /*---------------------------------------------------------------------------*/ 00155 #ifdef __cplusplus 00156 } 00157 #endif 00158 00159 /*---------------------------------------------------------------------------*/ 00160 #endif /* C54REGS__H */ 00161 00162 /***************************************************************************** 00163 Neuros Audio LLC. Confidential Proprietary 00164 *****************************************************************************/ 00165 00166
1.3.9.1