00001
00002
00003
00004
00005
00006
00007
00016
00017 #ifndef SYS_CPLD__H
00018 #define SYS_CPLD__H
00019
00020 #ifdef __cplusplus
00021 extern "C" {
00022 #endif
00023
00024
00025
00026
00027
00028
00029 ioport int port0000;
00030 ioport int port0001;
00031 ioport int port0002;
00032 ioport int port0003;
00033 ioport int port0004;
00034 ioport int port0005;
00035 ioport int port0006;
00036 ioport int port0007;
00037 ioport int port0008;
00038 ioport int port0009;
00039 ioport int port000a;
00040 ioport int port000b;
00041 ioport int port000c;
00042 ioport int port000d;
00043 ioport int port000e;
00044 ioport int port000f;
00045 ioport int port1000;
00046 ioport int port1001;
00047 ioport int port1002;
00048 ioport int port1003;
00049 ioport int port1004;
00050 ioport int port1005;
00051 ioport int port1006;
00052 ioport int port1007;
00053 ioport int port1008;
00054 ioport int port1009;
00055 ioport int port100a;
00056 ioport int port100b;
00057 ioport int port100c;
00058 ioport int port100d;
00059 ioport int port100e;
00060 ioport int port100f;
00061 ioport int port200f;
00062
00063 ioport int port8000;
00064 ioport int port8001;
00065 ioport int port800e;
00066 ioport int port800f;
00067
00068
00069 #define LED_KBD_ALL port0008 // LED for all keys except HISI.
00070 #define LED_KBD_HISI port1007 // LED for HiSi button.
00071
00072
00073 #define HDD_ID port800f
00074 #define SHUT_DOWN port1000
00075
00076
00077 #define RS_CTRL port100c // write to set; read to clear, don't care data
00078 #define LCD_ACCESS port100d // data and command access
00079
00080
00081 #define CPLD_CE0 port0003 // NAND FLASH device 0
00082 #define CPLD_CE1 port0004 // NAND FLASH device 1
00083 #define CPLD_CLE port0000 // NAND FLASH CLE
00084 #define CPLD_ALE port0001 // NAND FLASH ALE
00085 #define CPLD_nWP port0002 // NAND FLASH write protect
00086 #define CPLD_RDWR port0005 // active on READ on read or WRITE on write
00087
00088
00089
00090 #define TUNER_DAT port0006 // tuner data line
00091 #define TUNER_WR port000c // TUNER write/read line
00092 #define TUNER_CLK port000e // tuner clock
00093 #define TUNER_MOST port0007 // currently the same as the RTC enable line.
00094
00095
00096 #define RTC_EN port0007 // real time clock enable
00097
00098
00099 #define SPI_DATA port000a // SPI Data
00100 #define SPI_CLK port0009 // SPI Clock
00101 #define SPI_DIN port1009 // separate input data line for serial port
00102
00103
00104 #define CPLD_EN port000b // CPLD Enable line for SPI
00105 #define CODEC_EN port000d // codec enable line
00106 #define CPLD_CLKCTRL port1001 // when set, CPLD clock is on and set to 6 MHz
00107 #define CODEC_CLKSRC port1002 // selects CODEC clock, 0 = 12 MHz system clock
00108
00109
00110
00111
00112
00113 #define SYS_isHPpresent() ((port100e)&0x01)
00114 #define SYS_isLIpresent() ((port100f)&0x01)
00115
00116
00117 #define USB_CE port000f // enables PDIUSBD12 on reads or writes
00118 #define CMD_port port200f
00119 #define DATA_port port000f
00120
00121
00122
00123 #define VCTRL_XMIT 0x80;
00124 #define VCTRL_TUNER 0x40;
00125
00126
00127
00128
00129 #ifdef __cplusplus
00130 }
00131 #endif
00132
00133
00134 #endif
00135
00136
00137
00138
00139